Tên: Zynq-7000 All Programmable SoC / AD9361 70MHz to 6GHz, Software-Defined Radio Evaluation Kit - Module thí nghiệm phát triển Software Defined Radio
Đơn giá: Liên hệ
Nhà cung cấp: Avnet. Hàng mới 100%.
Liên hệ: 0934 993 253
Mô tả kỹ thuật
Họ SOC: Zynq-7000, XC7Z020; AD9361
Phân loại: Kit phát triển
Kit bao gồm: Board; FMCOMMS3-EBZ FMC Module ISE WebPACK with ChipScope license (Device Locked); Two Pulse LTE blade antennas
Loại bộ nhớ: DDR3
Dung lượng bộ nhớ: 512MB
Cấu hình bộ nhớ: 256MB QSPI
Kết nối không dây: Software Defined Radio
GPIO: Có
USB: USB OTG; USB-Serial Bridge
Giao tiếp tiêu chuẩn: FMC LPC; Pmod; XADC
Chế độ hình ảnh: HDMI Output; VGA Ou tput; OLED Output
Giao tiếp thẻ nhớ: SD Card
Nhà sản xuất: Avnet Design Servic es - Custom
Product Description
Combining the Xilinx Zynq®-7000 All-Programmable SoC (ARM® dual-core Cortex™-A9 + 28nm programmable logic) with the Analog Devices AD-FMCOMMS2-EBZ FMC module featuring the AD9361 integrated RF Agile Transceiver, the kit enables a broad range of transceiver applications for wireless communications. The kit is ideal for the wireless communications system architect seeking a unified development platform which operates over a wide RF tuning range from 70 MHz – 6 GHz.
Key Features & Benefits
Combines Xilinx Zynq-7000 All Programmable SoC ZC706 Evaluation Kit with Analog Devices AD9361 integrated RF Agile Transceiver
Includes schematics, layout, BOM, HDL, Linux drivers and application software
Optional MathWorks tools support for communications system design
Powered from single FMC connector
RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
SPI access for all device registers
Software tunable across wide frequency range (70MHz to 6GHz)
Supports MIMO radio, with less than 1 sample sync on both ADC and DAC
Supports add on cards for spectrum specific designs (PA, LNA etc)
Tunable channel bandwidth at the data converter: <200 kHz to 56 MHz
What's Included
8 GB SD card
AD-FMCOMMS3-EBZ
Four Pulse antennas LTE blade antennas (698-960/1710-2170/2500-2700 MHz)
Mã hàng: DE0-Nano-SoC Kit/Atlas-SoC Kit - Cyclone V Development Kit
Đơn giá: Liên hệ
Nhà sản xuất: Terasic. Hàng mới 100%.
Tên hàng:DE0-Nano-SoC Kit - P0286 /Atlas-SoC Kit - P0419
Tình trạng: Liên hệ
Liên hệ: 0934 993 253
Overview
The DE0-Nano-SoC Development Kit presents a robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE0-Nano-SoC development board is equipped with high-speed DDR3 memory, analog to digital capabilities, Ethernet networking, and much more that promise many exciting applications. The DE0-Nano-SoC Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later.
Specification
The DE0-Nano-SoC board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects. The following hardware is provided on the board: FPGA Device
Altera Cyclone® V SE 5CSEMA4U23C6N device
Serial configuration device – EPCS128
USB-Blaster II onboard for programming; JTAG Mode
2 push-buttons
4 slide switches
8 green user LEDs
Three 50MHz clock sources from the clock generator
Two 40-pin expansion header
One Arduino expansion header (Uno R3 compatibility), can connection with Arduino shields.
One 10-pin Analog input expansion header. (shared with Arduino Analog input)
A/D converter, 4-pin SPI interface with FPGA
HPS (Hard Processor System)
925MHz Dual-core ARM Cortex-A9 processor
1GB DDR3 SDRAM (32-bit data bus)
1 Gigabit Ethernet PHY with RJ45 connector
USB OTG Port, USB
Micro-AB connector Micro SD card socket
Accelerometer (I2C interface + interrupt)
UART to USB, USB Mini-B connector
Warm reset button and cold reset button
One user button and one user LED
LTC 2x7 expansion header
Block Diagram of the DE0-Nano-SOC Board
Connectivity
Connect LT24
Connect Arduino
Layout
Size：68.59x96mm
Resources
DE0-Nano-SoC Resources
Documents
Title
Version
Size(KB)
Date Added
Download
DE0-Nano-SoC QSG
1.0.0
2485
2015-05-21
DE0-Nano-SoC User Manual
1.5
7619
2015-12-29
CD-ROM
Title
Version
Size(KB)
Date Added
Download
DE0-Nano-SoC CD-ROM
1.1.0
-
2015-12-29
Reference Designs with Selected Daughter Cards
Daughter Board
Version
Size(KB)
Date Added
Download
LT24
1.0.0
-
2015-06-02
Arduino 1.8" TFT
1.0.0
-
2015-06-02
Linux BSP (Board Support Package): MicroSD Card Image
What's different between the DE0-Nano-SoC kit and the Atlas-SoC kit? The DE0-Nano-SoC kit uses the same printed circuit board as the Altas-SoC development platform. The only difference is the getting-started process for the two kits. Both kits come with a unique set of reference designs, tools, and documentation providing very different user experiences. Here's how to decide which is better for you: DE0-Nano-SoC: Designed for the hardware developer. It provides reference designs and tutorials to guide you through your first FPGA, HPS, and system designs. Atlas-SoC: Designed for the embedded software developer. It boots Linux, runs web and VNC servers, and provides reference designs, development tools, and tutorials to accelerate the learning curve of developing software for SoCs. Can’t decide which to use? Here’s how to get them both. Regardless of which kit you have, the reference designs, tools, documentation, and SD card images are available for free download. Because the hardware is the same, you can turn a DE0-Nano-SoC kit into an Atlas-SoC kit , or visa-versa, with a simple download and flash card update. Here's where to get the kit"soft" content: For more details on the Atlas-SoC kit, please visit: http://www.rocketboards.org/atlas-soc
Demo
If the film is unavailable, please kindly try another link below:
Mã hàng: P0159. [DE1-SOC] ALTERA Cyclone V SOC Development Kit
Xuất sứ: Taiwan.
Đơn giá: Liên hệVND
Nhà sản xuất: Terasic. Hàng mới 100%.
Tên hàng: DE1 Soc Board
Tình trạng: Liên hệ
Tấm mạch in đã được lắp ráp hoàn chỉnh dùng cho thiết bị phát triển hệ thống nhúng trên FPGA
Liên hệ: 0935 408 286 or 0934 993 253
Overview
The DE1-SoC Development Kit presents a robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE1-SoC development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more.
The DE1-SOC Development Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later ( 64-bit OS and Quartus II 64-bit are required to compile projects for DE1-SoC ).
Specification
The DE1-SoC board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.
The following hardware is provided on the board:
FPGA Device
Cyclone V SoC 5CSEMA5F31C6 Device
Dual-core ARM Cortex-A9 (HPS)
85K Programmable Logic Elements
4,450 Kbits embedded memory
6 Fractional PLLs
2 Hard Memory Controllers
Configuration and Debug
Quad Serial Configuration device – EPCQ256 on FPGA
On-Board USB Blaster II (Normal type B USB connector)
Memory Device
64MB (32Mx16) SDRAM on FPGA
1GB (2x256Mx16) DDR3 SDRAM on HPS
Micro SD Card Socket on HPS
Communication
Two Port USB 2.0 Host (ULPI interface with USB type A connector)
USB to UART (micro USB type B connector)
10/100/1000 Ethernet
PS/2 mouse/keyboard
IR Emitter/Receiver
Connectors
Two 40-pin Expansion Headers (voltage levels: 3.3V)
One 10-pin ADC Input Header
One LTC connector (One Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO interface)
Display
24-bit VGA DAC
Audio
24-bit CODEC, Line-in, line-out, and microphone-in jacks
Video Input
TV Decoder (NTSC/PAL/SECAM) and TV-in connector
ADC
Fast throughput rate: 1 MSPS
Channel number: 8
Resolution: 12 bits
Analog input range : 0 ~ 2.5 V or 0 ~ 5V as selected via the RANGE bit in the control register
Switches, Buttons and Indicators
4 User Keys (FPGA x4)
10 User switches (FPGA x10)
11 User LEDs (FPGA x10 ; HPS x 1)
2 HPS Reset Buttons (HPS_RST_n and HPS_WARM_RST_n)
Six 7-segment displays
Sensors
G-Sensor on HPS
Power
12V DC input
Block Diagram of the DE1-SOC Board
Layout
Size：166*130 mm
Resources
How to distinguish Rev B, Rev C and Rev D board?
Simply check the serial number on the board. Rev B
Rev C
Rev D
What is the part that has been changed?
The JTAG chain has been changed.For Rev C and Rev D board, the HPS comes before FPGA in the JTAG chain.
This is to bypass a bug in the DS-5 where reset can't function properly.
The difference between DE1-SoC Rev C and Rev D:
Both 5V and GPIO 3.3V power are provided by two different power module LTM4624 respectively in Rev C. In Rev D, 5V power is provided by one LTC3605 regulator instead of LTC4624, GPIO 3.3V power is provided by one original on-board LTC3605 regulator which provides all 3.3V power for DE1-SoC board.
Rev B JTAG chain: USB Blaster II ---> FPGA ---> HPS ---> USB Blaster II
Rev C and Rev D JTAG chain: USB Blaster II ---> HPS ---> FPGA ---> USB Blaster II
Changes in the CD-ROM
Item
Description
Schematic
JTAG Chain
User Manual
Modified Figures involving Quartus Programming and JTAG description
Demonstration Code
Batch file can automatically detect FPGA device index such that the code can be used for both revision boards.
Documents
Title
Version
Size(KB)
Date Added
Download
DE1-SoC User Manual(rev.C/rev.D Board)
1.1
10829
2014-06-11
DE1-SoC User Manual(rev.B Board)
1.0
9830
2014-02-07
DE1-SoC Learning Roadmap
1.0
2079
2014-02-07
BSP(Board Support Package) for Altera SDK OpenCL 14.0
Title
Linux Kernel
Size(KB)
Date Added
Download
DE1-SoC_openCL_BSP(.zip)
3.12
84.1 MB
2014-09-25
DE1-SoC_openCL_BSP(.tar.gz)
3.12
84.3 MB
2014-10-17
CD-ROM
Title
Version
Size(KB)
Date Added
Download
Quartus Download
2013-12-26
DE1SoC SystemBuilder
1.0.2
2014-10-03
DE1-SoC CD-ROM (rev.B Board)
1.2.0
2014-03-25
DE1-SoC CD-ROM (rev.C/rev.D Board)
3.1.0
2014-08-25
( 64-bit OSand Quartus II 64-bit are required to compile projects for DE1-SoC)
Linux BSP (Board Support Package): MicroSD Card Image
0
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