19/3/16

Kit DE1-SoC Board - Mạch Thí Nghiệm FPGA

(Cyclone V Starter Kit)
  • Mã hàng: P0159[DE1-SOC] ALTERA Cyclone V SOC Development Kit
  • Xuất sứ: Taiwan.
  • Đơn giá:  Liên hệ VND
  • Nhà sản xuất: Terasic. Hàng mới 100%.
  • Tên hàng: DE1 Soc Board
  • Tình trạng: Liên hệ
  • Tấm mạch in đã được lắp ráp hoàn chỉnh dùng cho thiết bị phát triển hệ thống nhúng trên FPGA
  • Liên hệ: 0935 408 286 or 0934 993 253

Overview



The DE1-SoC Development Kit presents a robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE1-SoC development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more.

The DE1-SOC Development Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later ( 64-bit OS and Quartus II 64-bit are required to compile projects for DE1-SoC  ).


Specification

The DE1-SoC board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects.

The following hardware is provided on the board:

FPGA Device
  • Cyclone V SoC 5CSEMA5F31C6 Device
  • Dual-core ARM Cortex-A9 (HPS)
  • 85K Programmable Logic Elements
  • 4,450 Kbits embedded memory
  • 6 Fractional PLLs
  • 2 Hard Memory Controllers
Configuration and Debug
  • Quad Serial Configuration device – EPCQ256 on FPGA
  • On-Board USB Blaster II (Normal type B USB connector)
Memory Device
  • 64MB (32Mx16) SDRAM on FPGA
  • 1GB (2x256Mx16) DDR3 SDRAM on HPS
  • Micro SD Card Socket on HPS
Communication
  • Two Port USB 2.0 Host (ULPI interface with USB type A connector)
  • USB to UART (micro USB type B connector)
  • 10/100/1000 Ethernet
  • PS/2 mouse/keyboard
  • IR Emitter/Receiver
Connectors
  • Two 40-pin Expansion Headers (voltage levels: 3.3V)
  • One 10-pin ADC Input Header
  • One LTC connector (One Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO interface)
Display
  • 24-bit VGA DAC
Audio
  • 24-bit CODEC, Line-in, line-out, and microphone-in jacks
Video Input
  • TV Decoder (NTSC/PAL/SECAM) and TV-in connector
ADC
  • Fast throughput rate: 1 MSPS
  • Channel number: 8
  • Resolution: 12 bits
  • Analog input range : 0 ~ 2.5 V or 0 ~ 5V as selected via the RANGE bit in the control register
Switches, Buttons and Indicators
  • 4 User Keys (FPGA x4)
  • 10 User switches (FPGA x10)
  • 11 User LEDs (FPGA x10 ; HPS x 1)
  • 2 HPS Reset Buttons (HPS_RST_n and HPS_WARM_RST_n)
  • Six 7-segment displays
Sensors
  • G-Sensor on HPS
Power
  • 12V DC input
Block Diagram of the DE1-SOC Board



Layout


  • Size:166*130 mm

Resources

How to distinguish Rev B, Rev C and Rev D board?
Simply check the serial number on the board.

 Rev B

 Rev C

 Rev D


What is the part that has been changed?

The JTAG chain has been changed.For Rev C and Rev D board, the HPS comes before FPGA in the JTAG chain.
This is to bypass a bug in the DS-5 where reset can't function properly.

The difference between DE1-SoC Rev C and Rev D:
Both 5V and GPIO 3.3V power are provided by two different power module LTM4624 respectively in Rev C. In Rev D, 5V power is provided by one LTC3605 regulator instead of LTC4624, GPIO 3.3V power is provided by one original on-board LTC3605 regulator which provides all 3.3V power for DE1-SoC board.

Rev B JTAG chain: USB Blaster II ---> FPGA ---> HPS ---> USB Blaster II


Rev C and Rev D JTAG chain: USB Blaster II ---> HPS ---> FPGA ---> USB Blaster II


Changes in the CD-ROM

ItemDescription
SchematicJTAG Chain
User ManualModified Figures involving Quartus Programming and JTAG description
Demonstration CodeBatch file can automatically detect FPGA device index such that the code can be used for both revision boards.

Documents

TitleVersionSize(KB)Date AddedDownload
DE1-SoC User Manual(rev.C/rev.D Board)1.1108292014-06-11
DE1-SoC User Manual(rev.B Board)1.098302014-02-07
DE1-SoC Learning Roadmap1.020792014-02-07

BSP(Board Support Package) for Altera SDK OpenCL 14.0

TitleLinux KernelSize(KB)Date AddedDownload
DE1-SoC_openCL_BSP(.zip)3.1284.1 MB2014-09-25
DE1-SoC_openCL_BSP(.tar.gz)3.1284.3 MB2014-10-17

CD-ROM

TitleVersionSize(KB)Date AddedDownload
Quartus Download2013-12-26
DE1SoC SystemBuilder1.0.22014-10-03
DE1-SoC CD-ROM (rev.B Board)1.2.02014-03-25
DE1-SoC CD-ROM (rev.C/rev.D Board)3.1.02014-08-25
 64-bit OS and Quartus II 64-bit  are required to compile projects for DE1-SoC  ) 

Linux BSP (Board Support Package): MicroSD Card Image

TitleLinux KernelMin. microSD CapacitySize(KB)Date AddedDownload
Linux Console3.124GB664952014-01-14
Linux Console with framebuffer3.124GB3285242014-03-24
Linux LXDE Desktop3.128GB 13695262014-03-21
Linux Ubuntu Desktop3.128GB11360752014-02-11


Compare



Demo
Innovate with Altera DE1-SoC Board



DE1-SoC-MTL2 Demonstration

Demonstration

TitleVersionSize(KB)Date AddedDownload
Download source code of VIP Demonstration-136MB2014-02-25

Kit Contents



  • DE1-SoC Board
  • DE1-SoC Quick Start Guide
  • Type A to B USB Cable
  • Type A to Mini-B USB Cable
  • Power DC Adapter (12V)

Nguồn Terasic

 

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